Field of the Invention
The present invention relates to a display device.
Discussion of the Related Art
With continuous development in an information society, the demand for various types of display devices to display an image is increasing. Various flat panel displays such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display have been recently used.
FIG. 1 illustrates a portion of a flat panel display. As shown in FIG. 1, the flat panel display includes a display panel DIS, a gate driver integrated circuit (IC), a source driver IC, etc. The display panel DIS includes gate lines GL1 to GLm, data lines DL1 to DLn, and pixels P arranged in a matrix form. Each of the pixels P of the display panel DIS receives data voltages supplied to the data lines DL1 to DLn from the source driver IC in response to gate signals supplied to the gate lines GL1 to GLm from the gate driver IC, thereby displaying an image.
The source driver IC is connected to data link lines DLL1 to DLLn through data pads DP1 to DPn, and the data lines DL1 to DLn are connected to the data link lines DLL1 to DLLn. Namely, the data link lines DLL1 to DLLn are connected between the data pads DP1 to DPn and the data lines DL1 to DLn. The data voltages from the source driver IC are supplied to the data lines DL1 to DLn through the data link lines DLL1 to DLLn. The data link lines DLL1 to DLLn are formed in a non-display area NAA of the display panel DIS, and the data lines DL1 to DLn are formed in a display area AA of the display panel DIS.
The gate driver IC is connected to gate link lines GLL1 to GLLm through gate pads GP1 to GPm, and the gate lines GL1 to GLm are connected to the gate link lines GLL1 to GLLm. Namely, the gate link lines GLL1 to GLLm are connected between the gate pads GP1 to GPm and the gate lines GL1 to GLm. The gate signals from the gate driver IC are supplied to the gate lines GL1 to GLm through the gate link lines GLL1 to GLLm. The gate link lines GLL1 to GLLm are formed in the non-display area NAA of the display panel DIS, and the gate lines GL1 to GLm are formed in the display area AA of the display panel DIS.
Because the source driver IC is generally designed to be smaller than the display panel DIS, a distance between the data pads DP1 to DPn is designed to be less than a distance between the data lines DL1 to DLn. Hence, the data link lines DLL1 to DLLn have different lengths as shown in FIG. 1. In general, a resistance of each of the data link lines DLL1 to DLLn is proportional to a length of each data link line and is inversely proportional to a cross-sectional area of each data link line. Namely, the resistance of each data link line varies depending on the length of each data link line. Hence, there is a difference between the resistances of the data link lines DLL1 to DLLn. Even if the source driver IC supplies the same data voltage to the data lines DL1 to DLn, a difference between the data voltages supplied to the data lines DL1 to DLn may be generated because of the resistance difference between the data link lines DLL1 to DLLn. Further, it is difficult to reduce a resistance difference between the gate link lines GLL1 to GLLm in the same manner as the data link lines DLL1 to DLLn.